ST10F271 datasheet(168/173 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F271

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Table 82.

SSC slave mode timings

Symbol

Parameter

Max. Baudrate

6.6 MBd (1))

@FCPU = 40MHz

(<SSCBR> = 0002h)

Variable Baudrate

(<SSCBR> = 0001h -

FFFFh)

Unit

min.

max.

min.

max.

t310

SR SSC clock cycle time(2)

150

8TCL

262144 TCL

t311

SR SSC clock high time

–

t310 / 2 – 12

–

t312

SR SSC clock low time

–

t310 / 2 – 12

–

t313

SR SSC clock rise time

–

t314

SR SSC clock fall time

–

t315

CC Write data valid after shift edge

–

2TCL + 30

t316

CC Write data hold after shift edge

–

t317p

Read data setup time before latch

edge, phase error detection on

(SSCPEN = 1)

–

4TCL + 12

–

t318p

Read data hold time after latch

edge, phase error detection on

(SSCPEN = 1)

–

6TCL + 12

–

t317

Read data setup time before latch

edge, phase error detection off

(SSCPEN = 0)

6–

–

t318

Read data hold time after latch

edge, phase error detection off

(SSCPEN = 0)

–

2TCL + 6

–

Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with

48MHz CPU clock and <SSCBR> set to ‘2h’. When 40MHz CPU clock is used the maximum baudrate cannot be higher

than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only

with CPU clock lower than 32MHz (after checking that resulting timings are suitable for the master).

Formula for SSC Clock Cycle time: t310 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer.

Minimum limit allowed for t310 is 125ns (corresponding to 8Mbaud).

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