PIC16F753 datasheet(48/230 Pages) MICROCHIP

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PIC16F753/HV753

DS40001709C-page 48

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5.7

Additional Pin Functions

Every PORTC pin on the PIC16F753 has an interrupt-

on-change option and a weak pull-up option. The next

three sections describe these functions.

5.7.1

ANSELC REGISTER

The ANSELC register (Register 5-5) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELC bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELC bits has no effect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

5.7.2

WEAK PULL-UPS

Each of the PORTC pins, except RC3, has an

individually configurable internal weak pull-up. Control

bits WPUx enable or disable each pull-up. Refer to

off when the port pin is configured as an output. The

pull-ups are disabled on a Power-on Reset by the

RAPU bit of the OPTION_REG register. A weak pull-up

is automatically enabled for RC3 when configured as

MCLR and disabled when RC3 is an I/O. There is no

software control of the MCLR pull-up.

5.7.3

INTERRUPT-ON-CHANGE

Each PORTC pin is individually configurable as an

interrupt-on-change pin. Control bit IOCC enables or

disables the interrupt function for each pin. Refer to

Power-on Reset.

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTC. The ‘mismatch’ outputs of the last read are

OR’d together to set the PORTC Change Interrupt Flag

bit (IOCIF) in the INTCON register (Register 2-3).

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, clears the

interrupt by:

Any read of PORTC AND Clear flag bit IOCIF.

This will end the mismatch condition;

Any write of PORTC AND Clear flag bit IOCIF

will end the mismatch condition;

A mismatch condition will continue to set flag bit IOCIF.

Reading PORTC will end the mismatch condition and

allow flag bit IOCIF to be cleared. The latch holding the

last read value is not affected by a MCLR nor BOR

Reset. After these Resets, the IOCIF flag will continue

to be set if a mismatch is present.

5.7.4

SLEW RATE CONTROL

Two of the PORTC pins, RC4 and RC5, are equipped

with high current driver circuitry. The SLRCONC register

provides reduced slew rate control to mitigate possible

EMI radiation from these pins.

Note:

The ANSELC bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

Note:

If a change on the I/O pin should occur

when any PORTC operation is being

executed, then the IOCIF interrupt flag

may not get set.

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