PIC16F753 datasheet(71/230 Pages) MICROCHIP

71 / 230 page

 2013-2015 Microchip Technology Inc.

DS40001709C-page 71

PIC16F753/HV753

9.1

HLT Operation

The clock input to the HLT module is the system

instruction clock (FOSC/4). HLTMRx increments on

each rising clock edge.

A 4-bit counter/prescaler on the clock input provides the

following prescale options:

• Direct input

•Divide-by-4

•Divide-by-16

•Divide-by-64

The prescale options are selected by the prescaler

control bits, HxCKPS<1:0> of the HLTxCON0 register.

The value of HLTMRx is compared to that of the Period

values match,then the comparator generates a match

signal as the HLTimerx output. This signal also resets

the value of HLTMRx to 00h on the next clock rising

edge and drives the output counter/postscaler (see

Section 9.2 “HLT Interrupt”).

The HLTMRx and HLTPRx registers are both directly

readable and writable. The HLTMRx register is cleared

on any device Reset, whereas the HLTPRx register

initializes to FFh. Both the prescaler and postscaler

counters are cleared on any of the following events:

• A write to the HLTMRx register

• A write to the HLTxCON0 register

• Power-on Reset (POR)

• Brown-out Reset (BOR)

•MCLR Reset

• Watchdog Timer (WDT) Reset

• Stack Overflow Reset

• Stack Underflow Reset

• RESET Instruction

9.2

HLT Interrupt

The HLT can also generate an optional device interrupt.

The HLTMRx output signal (HLTMRx-to-HLTPRx match)

provides the input for the 4-bit counter/postscaler. The

overflow output of the postscaler sets the HLTMRxIF bit

of the PIR1 register. The interrupt is enabled by setting

the HLTMRx Match Interrupt Enable bit, HLTMRxIE of

the PIE1 register.

A range of 16 postscale options (from 1:1 through 1:16

inclusive) can be selected with the postscaler control

bits, HxOUTPS<3:0>, of the HLTxCON0 register.

9.3

Peripheral Resets

Resets driven from the selected peripheral output pre-

vents the HLTMRx from matching the HLTPRx register

and generating an output. In this manner, the HLT can

be used as a hardware time limit to other peripherals.

In this device, the primary purpose of the HLT is to limit

the COG PWM duty cycle. Normally, the COG opera-

tion uses analog feedback to determine the PWM duty

cycle. The same feedback signal is used as an HLT

Reset input. The HLTPRx register is set to occur at the

maximum allowed duty cycle. If the analog feedback to

the COG exceeds the maximum time, then an

HLTMRx-to-HLTPRx match will occur and generate the

output needed to limit the COG drive output.

The HLTMRx can be reset by one of several selectable

peripheral sources. Reset inputs include:

• CCP1 output

• Comparator 1 output

• Comparator 2 output

• COGxFLT pin

• COG1OUT0

• COG1OUT1

The external Reset input is selected with the

HxERS<2:0> bits of the HLTxCON1 register. High and

low Reset enables are selected with the HxREREN and

HxFEREN bits, respectively. Setting the HxRES and

HxFES bits makes the respective rising and falling

Reset events edge sensitive. Reset inputs that are not

edge sensitive are level sensitive.

HLTMRx Resets are synchronous with the HLT clock.

In other words, HLTMRx is cleared on the rising edge

of the HLT clock after the enabled Reset event occurs.

If an enabled external Reset occurs at the same time a

write occurs to the TMR4A register, the write to the

timer takes precedence and pending Resets are

cleared.

9.4

HLTimerx Output

The unscaled output of HLTMRx is available only to the

COG module, where it is used as a selectable limit to

the maximum COG period.

9.5

HLT Operation During Sleep

The HLT cannot be operated while the processor is in

Sleep mode. The contents of the HLTMRx register will

remain unchanged while the processor is in Sleep

mode.

Note:

HLTMRx is not cleared when HLTxCON0 is

written.

PIC16F753 数据表(PDF) 71 Page - Microchip Technology

PIC16F753 数据表(HTML) 71 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载