PIC16F753 datasheet(91/230 Pages) MICROCHIP

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DS40001709C-page 91

PIC16F753/HV753

11.9

Buffer Updates

Changes to the phase, dead-band, and blanking count

registers need to occur simultaneously during COG

operation to avoid unintended operation that may

occur as a result of delays between each register

write. This is accomplished with the GxLD bit of the

COGxCON0 register and double buffering of the

phase, blanking, and dead-band count registers.

Before the COG module is enabled, writing the count

registers loads the count buffers without need of the

GxLD bit. However, when the COG is enabled, the

count buffers updates are suspended after writing the

count registers until after the GxLD bit is set. When the

GxLD bit is set, the phase, dead-band, and blanking

buffers synchronous with COG operation. The GxLD

bit is cleared by hardware when the transfer is

complete.

11.10 Alternate Pin Selection

The

COGxOUT0,

COGxOUT1

and

COGxFLT

functions can be directed to alternate pins with control

bits of the APFCON register. Refer to Register 5-1.

11.11 Operation During Sleep

The COG continues to operate in Sleep provided that

the COG_clock, rising event, and falling event sources

remain active.

The HFINTSOC remains active during Sleep when the

COG is enabled and the HFINTOSC is selected as the

COG_clock source.

11.12 Configuring the COG

The following steps illustrate how to properly configure

the COG to ensure a synchronous start with the rising

event input:

Configure

the

desired

COGxFLT

input,

COGxOUT0 and COGxOUT1 pins with the

corresponding bits in the APFCON register.

Clear all ANSELA register bits associated with

pins that are used for COG functions.

Ensure that the TRIS control bits corresponding

to COGxOUT0 and COGxOUT1 are set so that

both are configured as inputs. These will be set

as outputs later.

Clear the GxEN bit, if not already cleared.

Set desired dead-band times with the COGxDBR

and COGxDBF registers.

Set desired blanking times with the COGxBKR

and COGxBKF registers.

Set desired phase delay with the COGxPHR

and COGxPHF registers.

Select the desired shutdown sources with the

COGxASD1 register.

Set up the following controls in COGxASD0

auto-shutdown register:

• Select both output overrides to the desired

levels (this is necessary, even if not using

auto-shutdown because start-up will be from

a shutdown state).

• Set the GxASDE bit and clear the GxARSEN

bit.

10. Select the desired rising and falling event sources

with the COGxRIS and COGxFIS registers.

11. Select the desired rising and falling event modes

with the COGxRSIM and COGxFSIM registers.

12. Configure

the

following

controls

the

COGxCON1 register:

• Select the desired clock source

• Select the desired dead-band timing sources

13. Configure

the

following

controls

the

COGxCON0 register:

• Select the desired output polarities.

• Set the output enables of the outputs to be

used.

14. Set the GxEN bit.

15. Clear TRIS

control bits

corresponding to

COGxOUT0 and COGxOUT1 to be used,

thereby configuring those pins as outputs.

16. If auto-restart is to be used, set the GxARSEN bit

and the GxASDE will be cleared automatically.

Otherwise, clear the GxASDE bit to start the

COG.

Note:

The default COG outputs have high drive

strength capability, whereas the alternate

outputs do not.

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