PIC16F753 datasheet(70/230 Pages) MICROCHIP

70 / 230 page

PIC16F753/HV753

DS40001709C-page 70

 2013-2015 Microchip Technology Inc.

9.0

HARDWARE LIMIT TIMER (HLT)

MODULE

The Hardware Limit Timer (HLT) module is a version of

the Timer2-type modules. In addition to all the Timer2-

type features, the HLT can be reset on rising and falling

events from selected peripheral outputs.

The HLT primary purpose is to act as a timed hardware

limit to be used in conjunction with asynchronous

analog feedback applications. The external Reset

source synchronizes the HLTMRx to an analog

application.

In normal operation, the external Reset source from the

analog application should occur before the HLTMRx

matches the HLTPRx. This resets HLTMRx for the next

period and prevents the HLTimerx Output from going

active.

When the external Reset source fails to generate a

signal within the expected time, (allowing the HLTMRx

to match the HLTPRx), then the HLTimerx Output

becomes active.

The HLT module incorporates the following features:

• 8-bit Read-Write Timer Register (HLTMRx)

• 8-bit Read-Write Period register (HLTPRx)

• Software programmable prescaler:

-1:1

-1:4

-1:16

-1:64

• Software programmable postscaler

- 1:1 to 1:16, inclusive

• Interrupt on HLTMRx match with HLTPRx

• Eight selectable timer Reset inputs (two reserved)

• Reset on rising and falling event

Refer to Figure 9-1 for a block diagram of the HLT.

FIGURE 9-1:

HLTMRx BLOCK DIAGRAM

Comparator

HLTPRx

Detect

HLTMRx

CCP1 out

C1OUT

C2OUT

COG1FLT

COG1OUT0

COG1OUT1

‘0’

Fosc/4

HxON

HxRES

HxFES

HxFEREN

HxREREN

HLTMRxIF

HLT Output

To COG module

Prescaler

1:1, 1:4, 1:16, 1:64

Postscaler

1:1 to 1:16

Postscaler

1:1 to 1:16

HxOUTPS<3:0>

HxCKPS<1:0>

000

001

010

011

100

101

110

111

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