PIC16F753 datasheet(74/230 Pages) MICROCHIP

74 / 230 page

PIC16F753/HV753

DS40001709C-page 74

 2013-2015 Microchip Technology Inc.

10.0

CAPTURE/COMPARE/PWM

MODULES

The Capture/Compare/PWM module is a peripheral

which allows the user to time and control different

events, and to generate Pulse-Width Modulation

(PWM) signals. In Capture mode, the peripheral allows

the timing of the duration of an event. The Compare

mode allows the user to trigger an external event when

a predetermined amount of time has expired. The

PWM mode can generate Pulse-Width Modulated

signals of varying frequency and duty cycle.

10.1

Capture Mode

Capture mode makes use of the 16-bit Timer1

resource. When an event occurs on the CCP1 pin, the

16-bit CCPR1H:CCPR1L register pair captures and

stores the 16-bit value of the TMR1H:TMR1L register

pair, respectively. An event is defined as one of the

following and is configured by the CCP1M<3:0> bits of

the CCP1CON register:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

When a capture is made, the Interrupt Request Flag bit

CCP1IF of the PIR2 register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPR1H, CCPR1L register pair

is read, the old captured value is overwritten by the new

captured value.

Figure 10-1 shows a simplified diagram of the Capture

operation.

10.1.1

CCP1 PIN CONFIGURATION

In Capture mode, the CCP1 pin should be configured

as an input by setting the associated TRIS control bit.

FIGURE 10-1:

CAPTURE MODE

OPERATION BLOCK

DIAGRAM

10.1.2

TIMER1 MODE RESOURCE

Timer1 must be running in Timer mode or Synchronized

Counter mode for the CCP1 module to use the capture

feature. In Asynchronous Counter mode, the capture

operation may not work.

See Section 7.0 “Timer1 Module with Gate Control”

for more information on configuring Timer1.

10.1.3

SOFTWARE INTERRUPT MODE

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCP1IE interrupt enable bit of the PIE2 register clear to

avoid false interrupts. Additionally, the user should

clear the CCP1IF interrupt flag bit of the PIR2 register

following any change in Operating mode.

10.1.4

CCP1 PRESCALER

There are four prescaler settings specified by the

CCP1M<3:0>

bits

the

CCP1CON

Whenever the CCP1 module is turned off, or the CCP1

module is not in Capture mode, the prescaler counter

is cleared. Any Reset will clear the prescaler counter.

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCP1CON register before changing the

prescaler. Example 10-1 demonstrates the code to

perform this function.

EXAMPLE 10-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

Note:

If the CCP1 pin is configured as an output,

a write to the port can cause a capture

condition.

CCPR1H

CCPR1L

TMR1H

TMR1L

Set Flag bit CCP1IF

(PIR2 register)

Capture

Enable

CCP1M<3:0>

Prescaler

 1, 4, 16

and

Edge Detect

CCP1

System Clock (FOSC)

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Capture

mode. In order for Capture mode to

recognize the trigger event on the CCP1

pin, Timer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

BANKSEL CCP1CON

;Set Bank bits to point

;to CCP1CON

CLRF

CCP1CON

;Turn CCP1 module off

MOVLW

NEW_CAPT_PS ;Load the W reg with

;the new prescaler

;move value and CCP1 ON

MOVWF

CCP1CON

;Load CCP1CON with this

;value

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