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PIC16F753 数据表(PDF) 73 Page - Microchip Technology |
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PIC16F753 数据表(HTML) 73 Page - Microchip Technology |
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73 / 230 page  2013-2015 Microchip Technology Inc. DS40001709C-page 73 PIC16F753/HV753 TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH HLT REGISTER 9-2: HLTxCON1: HLTx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 HxFES HxRES — HxERS<2:0> HxFEREN HxREREN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 HxFES: Hardware Limit Timerx Falling Edge Sensitivity bit 1 = Edge sensitive 0 = Level sensitive bit 6 HxRES: Hardware Limit Timerx Rising Edge Sensitivity bit 1 = Edge sensitive 0 = Level sensitive bit 5 Unimplemented: Read as ‘0’ bit 4-2 HxERS<2:0>: Hardware Limit Timerx External Reset Source Select bits 000 = CCP1 Out 001 =C1OUT 010 =C2OUT 011 = COG1FLT 100 = COG1OUT0 101 = COG1OUT1 110 = Reserved - ‘0’ input 111 = Reserved - ‘0’ input bit 1 HxFEREN: Hardware Limit Timerx Falling Event Reset Enable bit 1 = HLTMRx will reset on the first clock after a falling event of selected Reset source 0 = Falling events of selected source have no effect bit 0 HxREREN: Hardware Limit Timerx Rising Event Reset Enable bit 1 = HLTMRx will reset on the first clock after a rising event of selected Reset source 0 = Rising events of selected source have no effect Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CCP1CON — — DC1B<1:0> CCP1M<3:0> 80 CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 129 CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> 130 CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 129 CM2CON1 C2INTP C2INTN C2PCH<2:0> C2NCH<2:0> 130 INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF 17 PIE1 TMR1GIE ADIE — — HLTMR2IE HLTMR1IE TMR2IE TMR1IE 18 PIR1 TMR1GIF ADIF — — HLTMR2IF HLTMR1IF TMR2IF TMR1IF 20 HLTMRx Holding Register for the 8-bit Hardware Limit TimerX Count 70* HLTPRx HLTMRx Module Period Register 70* HLTxCON0 — HxOUTPS<3:0> HxON HxCKPS<1:0> 72 HLTxCON1 HxFES HxRES — HxERS<2:0> HxFEREN HxREREN 73 Legend: — = unimplemented location, read as ‘0’. Shaded cells do not affect the HLT module operation. * Page provides register information. |
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