L9908 datasheet(64/152 Pages) STMICROELECTRONICS

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Symbol

Parameter

Test Condition

Min Typ Max Unit

Notes

DRV_ls_rpu

LS Pre-driver output

resistance at high state

IGLS_n = 4 mA

INLn = 1

[n = 1,2,3]

1.35 1.7 3.55

Ω

DRV_iout_reverse

Pre-driver reverse output

current

GHS_n-SHS_n = -0.6 V

GLS_n-SLS_n = -0.6 V

[n = 1,2,3]

Not subject to

production

test

Note:

All parameters are guaranteed, and tested, in the voltage ranges reported above in Table 5 unless otherwise

specified. Where not specified the parametrical operating range equals the functional operating range.

Note:

Given the standard Ext. FET model, the currents and voltages behavior at its terminals at Turn-on/off can be

described by the following piece-wise linear diagram.

Figure 37. Ext. FET Turn-on/off simplified behavior

Where:

1. The gate-source voltage (VGS) ramps up according to the time constant formed by the FET gate resistance

(Rg) and input capacitance (Ciss)

2. Once the VGS reaches the threshold voltage (Vth) the current through the device starts to ramp up. The

channel is supporting the full-load current and the drain-source voltage (VDS) starts decaying.

3. The VDS falls continuously to its on-state value while the VGS stays approximately constant (Miller Plateau)

as well as the gate current.

4. The VGS ramps up to the value applied by the driver. This additional gate voltage fully enhances the FET

channel and reaches the full RdsON.

Turn-off is the reverse of turn-on process. During turn-off, the Miller Plateau indicates the start of the rise of the

VDS and the voltage of the Miller Plateau will represent the minimum required VGS to sustain the load current.

While a precise value of FET`s VDS slew rates at turn-on/off requires simulations including FET and GDU model

plus the board and package parasitic details a first order approximations can be used to estimate this value.

The key parameter required for the estimation is the peak current the driver can source/sink to the Ext. FET gate

terminal during the turn-on/off process, so the FET VDS rise/fall time can then be approximated by:

trise= Qgd

IDRV_SOURCE_PEAK

(6)

tfall= Qgd

IDRV_SINK_PEAK

(7)

L9908

Functional description

DS13546 - Rev 5

page 64/152

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