L9908 datasheet(41/152 Pages) STMICROELECTRONICS

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5.6.3

Half bridges disable logic

The enabling/disabling operation of the n-th Half Bridges is managed by a dedicated combinatory disable logic

which constantly processes the following disable sources:

•

HBn_DIS SPI configuration register status

•

EN_BR pin status

•

STD faults detection

•

VPRE UV fault detection

•

NDIS pin state

•

Configurable reaction faults detection with related FRC set as 00 or 01

The status of the n-th disable n-th half bridge is echoed into dedicated SPI readable registers: HBn_EN_ECHO [n

= 1, 2, 3].

5.6.4

Gate driver supply enable logic

The enabling/disabling operation of the Gate Driver supply unit (CP1 and CP2) is managed by a dedicated

combinatory disable logic which constantly processes the following disable sources:

•

CP1_DIS & CP2_DIS SPI bits status (within register SAFETY_RELEVANT3)

•

STD faults detection

•

NDIS pin status

•

Configurable reaction faults detection with related FRC set as 00

The status of the n-th charge pump is echoed into dedicated SPI signals CPn_EN_ECHO [n = 1,2,3], within

L9908

Functional description

DS13546 - Rev 5

page 41/152

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