L9908 datasheet(66/152 Pages) STMICROELECTRONICS

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5.12.1

External FET VGS monitor

The correct functionality of each of the six pre-drivers is monitored by a dedicated comparator that senses the

difference between gate and source terminals of the Ext. FET.

If GHS_n-SHS_n (GLS_n-SLS_n) ≥ VGS_TH + VGS_uv_hys occurs for an interval longer than T_vgs_flt the VGS

comparator output goes to 0 and the HSn_OFF (LSn_OFF) flag is reset. The external FET is considered turned-

on.

If GHS_n-SHS_n (GLS_n-SLS_n) ≤ VGS_TH occurs for an interval longer than T_vgs_flt the VGS comparator

output goes to 1 and the HSn_OFF (LSn_OFF) flag is set. The external FET is considered turned-off.

Table 60. VGS monitor electrical characteristics

Symbol

Parameter

Min

Typ

Max

Unit

Notes

VGS_mon_th

VGS monitor threshold

2.5

VGS_uv_hys

VGS monitor hysteresis

200

T_vgs_uv_flt

VGS monitor detection filter time

200

230

300

Analog filter

Note:

All parameters are guaranteed, and tested, in the voltage ranges reported above in Table 5 unless otherwise

specified. Where not specified the parametrical operating range equals the functional operating range.

Figure 39. VGS monitor operative ranges

5.12.2

Dead Time Protection (DTP)

The prevention of cross-conduction due to HSn/LSn ON-phase overlap is in principle under the responsibility of

the uC driving the PWM pins INHn/INLn. However, a built-in dead time protection is available.

When the main logic processes a falling edge event on INHn/INLn it starts a programmable masking time interval

T_dead_flt during which the rising edges on the opposite signal (INLn/INHn respectively) are ignored.

In general a rising edge on INHn/INLn is processed only during the condition INHn=INLn= 0 and if such a

condition hold for at least a T_dead_flt.

L9908

Functional description

DS13546 - Rev 5

page 66/152

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