L9908 datasheet(79/152 Pages) STMICROELECTRONICS

79 / 152 page

5.13.2.1

Low-pass filtering

The first operation performed is a 2nd order low-pass filtering on the raw ADC data accomplished by two

cascaded single pole filters with the same cut-off frequency.

Figure 53. Digital LP filtering simplified block diagram

The filter`s cut-off frequency can be configured through SPI as follows (setting is common for the three phases):

Table 73. Current monitors LP filtering configuration bits

CSM_LP_CFG2

CSM_LP_CFG1

CSM_LP_CFG0

Description

No filtering (Default)

91 kHz

37 kHz

17 kHz

8 kHz

4 kHz

2 kHz

1 kHz

5.13.2.2

Conversion sampling

Current monitor`s DSP allows two kinds of data flow toward the SPI register (digital format) and to D/A (analog

format):

•

Free running;

•

Track & Hold

Note:

Conversion sampling affects NO A/D operation whatsoever. Conversion sampling logic only defines how SPI

reg. and D/A output values have to be updated.

5.13.2.2.1

Free running

In Free Running mode the CSn_READ SPI registers and the CSOn voltage are continuously updated as soon as

A/D output words are available.

Free Running mode is enabled configuring signal CSM_SAMPLE_CFG = 000 in the register CHn_CFG2.

Note:

In the following timing diagrams, N-th A/D Out value corresponds to the SAR conversion value.

L9908

Functional description

DS13546 - Rev 5

page 79/152

L9908 数据表(PDF) 79 Page - STMicroelectronics

L9908 数据表(HTML) 79 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载