L9908 datasheet(27/152 Pages) STMICROELECTRONICS

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2. NVM READ MODE

Internal supply and reference voltage/currents are available possibly exceeding spec parametrical ranges. The

main logic is out of reset (INT_RST = ’1’, internal signal). Main functions are disabled:

–

Gate driver supply stage disabled

–

Half Bridge gate drivers stages are in HIZ mode while LS half Bridge gate drivers stages are shutdown

(SAFE-HIZ)

–

Current monitors chains and monitoring units are disabled

–

SPI Read is available while SPI write is disabled

In this mode a CRC check on NVM data is first performed:

–

If no CRC error is detected the NVM content is deployed into main logic register

–

If a CRC error is detected the related main logic registers are reset to default values (all ‘0’) and

NVM_CRC_FAIL flag is set to ‘1’

Note:

All parameters are guaranteed and tested in the voltage ranges reported in Table 5 unless otherwise

specified. Where not specified the parametrical operating range equals the functional operating range.

Table 15. Power up/down timings

Symbol

Parameter

Min

Typ

Max Unit

Notes

T_nvm

NVM data deploy & CRC duration

Not subject to production test

3. NORMAL MODE

Internal supply and reference voltage/currents are available and within spec ranges. The main logic is out of

reset (INT_RST = ’1’, internal signal). Main functions:

–

Half Bridge gate drivers status depends on disable logic assessment (Functional or SAFE_DIS)

–

Gate driver supply stage status depends on configuration

–

Current monitors chains and monitoring units status depend on configuration

–

SPI Read/Write operations are available

4. SAFE OFF MODE

Internal supply and reference voltage/currents are available and within spec ranges. The main logic is out of

reset (INT_RST = ’1’, internal signal). Main functions:

–

Gate driver supply stage is disabled

–

HS and LS states are in SAFE_OFF or SAFE_HIZ depending on fault reaction as described in Table 17

–

Current monitors chains and monitoring units status depend on configuration

–

SPI Read/Write operations are available

5. SELF TEST MODE

Internal supply and reference voltage/currents are available and within spec ranges. The main logic is out of

reset (INT_RST = ’1’, internal signal). Main functions:

–

Gate driver supply stage depends on disable logic assessment

–

Half Bridge gate drivers are disabled (SAFE-DIS)

–

Current monitors chains and monitoring units status depend on configuration

–

SPI Read is available while SPI write is disabled

6. CONFIG MODE

Internal supply and reference voltage/currents are available and within spec ranges. The main logic is out of

reset (INT_RST = ’1’, internal signal). Main functions:

–

Half Bridge gate drivers status depends on disable logic assessment (Functional or SAFE_DIS)

–

Gate driver supply stage status depends on configuration

–

Current monitors chains and monitoring units status depend on configuration

–

SPI Read/Write operations are available

Three SPI readable flags are present to read-back the operational state machine status according to the following

table:

L9908

Functional description

DS13546 - Rev 5

page 27/152

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