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L9908 数据表(PDF) 28 Page - STMicroelectronics |
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L9908 数据表(HTML) 28 Page - STMicroelectronics |
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28 / 152 page  Table 16. Operation mode status bits OPERATION_MODE2 OPERATION_MODE1 OPERATION_MODE0 Description 0 0 0 RESET mode 0 0 1 NVM Read mode 0 1 0 SAFE OFF mode 0 1 1 NORMAL mode 1 0 0 CFG mode 1 0 1 SELF TEST mode 1 1 0 RESET mode 1 1 1 RESET mode Table 17. Device operation modes summary Operation mode Logic Core Gate driver supply HS/LS pre-drivers Current Monitors Diagnosis SPI access RESET Reset Disabled SAFE_HIZ Disabled Disabled Disabled NVM READ Functional Disabled SAFE_HIZ Disabled Disabled Read SELF TEST Functional As configured SAFE_DIS As configured As configured Read SAFE OFF Functional Disabled SAFE_OFF/ SAFE_HIZ Disabled As configured Read/Write CONFIG Functional As configured Functional/SAFE_DIS As configured As configured Read/Write NORMAL Functional As configured Functional/SAFE_DIS As configured As configured Read/Write 5.4 Configuration mode The L9908 default configuration can be modified by properly writing the SPI configuration registers. Configuration registers are divided into three categories depending on their functional safety relevance: • Safety Relevant Registers (SRR): the content of these registers is protected by a two-step LOCK mechanism: CONFIG mode access procedure and a masking related to Half Bridges status (EN_BR = 0 or HBn_DIS = 1 with n = 1, 2, 3). The content is then protected by a cyclic 5-bit CRC check. • Safety Latent Registers (SLR): the content of these registers is protected by a one-step LOCK mechanism: CONFIG mode access procedure. The content has no CRC protection. • Non-safety Registers (NSR): the content of these registers can be accessed directly in NORMAL Mode and has no CRC protection. Correct SRR modification is safety relevant and then a CRC check on their bit is performed continuously by a dedicated state machine. CRC check is performed sequentially over the 11 bits content of shadow register, LSB first. The 5-bit CRC is calculated using the following polynomial expression over bit 5-15: gx =x5+x2+1 (4) The initial value to be used is 11111 (0x1F). Example: • Input word: [000.0000.0100] (0x004) • Computed CRC: [0.1011] (0XB) • Resulting frame: [0000.0000.1000.1011] (0X8B) If a CRC violation on one or more SRR the SR_CRC_FAIL flag is set. The error flag remains set until the failure condition is removed and the flag is cleared by the SPI command. L9908 Functional description DS13546 - Rev 5 page 28/152 |
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