L9908 datasheet(30/152 Pages) STMICROELECTRONICS

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Table 19. CFG timeout

Symbol

Parameter

Min

Typ

Max

Unit

Notes

T_cgf_time_out

CFG mode Time-out

100

Not subject to production test

5.5

Self-test mode

A built-in self-test (BIST) procedure is implemented to check safety relevant circuitries both in digital core and in

the analog monitor circuits on L9908.

The target of core logic self-test is to check the correct functionality of the Internal Clock Monitor.

The target of the analog monitor is to check the correct functionality of the comparators involved in the safety

relevant monitors and of the Safety Switch Off path.

To allow a certain amount of freedom the block on which the self-test procedure runs can be configured by setting

a dedicated SPI frame.

Note:

•

During Self-Test of the SW OFF path SAFE-OFF state is activated

•

In case of BIST_STATUS = 11 (BIST check failure), the device is sent in SAFE_OFF Mode; re-engage

procedure can be performed only by issuing a SW_RESET command

Table 20. Self-test selection bits

SELF_TEST_CFG4 SELF_TEST_CFG3 SELF_TEST_CFG2 SELF_TEST_CFG1

SELF_TEST

_CFG0

Description

OND LS

OND HS

Supply Monitors

SW OFF Path

Clock Monitor

Self-Test Not

Active

Self-Test Active

(Defaults)

Note:

Supply Monitors include: Internal Supply, VDD, VPRE, VCP, VBP, VDH and GLM.

Self-Test procedure is developed in different steps in the following order:

•

Clock Monitor

•

Supply Monitor & OND_LS & OND_HS

•

SW OFF Path

5.5.1

Self-test activation

When Self-Test procedure is active, safety related analog and digital parts are under test, thus are not functional;

this implies that Self-Test procedure can be activated only when no actuation is applied to half bridges:

HBn_DIS = 1 [n = 1, 2, 3] or EN_BR = 0.

Accidental Self-Test procedure activation must be avoided therefore a finite state machine is implemented. The

Self-Test activation state machine is composed by 2 sequential states, the passage from a state to the next one is

carried out by a correct Self-Test activation SPI frame sequence to be written in the SPI register BIST_KEY

(SELF-TEST1 key: 0x55 → SELF-TEST 2 key: 0x33).

Table 21. Self-test mode activation register

BIST_KEY <7:0>

Description

0x55à0x33

SELF TEST Mode Access

L9908

Functional description

DS13546 - Rev 5

page 30/152

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