ST72E331 datasheet(66/107 Pages) STMICROELECTRONICS

66 / 107 page

66/107

ST72E331 ST72T331

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.5.7 Register Description

STATUS REGISTER (SR)

Read Only

Reset Value: 1100 0000 (C0h)

Bit 7 = TDRE

Transmit data register empty.

This bit is set by hardware when the content of the

TDR register has been transferred into the shift

the CR2 register. It is cleared by a software se-

quence (an access to the SR register followed by a

write to the DR register).

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

Note: data will not be transferred to the shift regis-

ter as long as the TDRE bit is not reset.

Bit 6 = TC

Transmission complete.

This bit is set by hardware when transmission of a

frame containing Data, a Preamble or a Break is

complete. An interrupt is generated if TCIE=1 in

the CR2 register. It is cleared by a software se-

quence (an access to the SR register followed by a

write to the DR register).

0: Transmission is not complete

1: Transmission is complete

Bit 5 = RDRF

Received data ready flag.

This bit is set by hardware when the content of the

RDR register has been transferred into the DR

CR2 register. It is cleared by a software sequence

(an access to the SR register followed by a read to

the DR register).

0: Data is not received

1: Received data is ready to be read

Bit 4 = IDLE

Idle line detect.

This bit is set by hardware when a Idle Line is de-

tected. An interrupt is generated if the ILIE=1 in

the CR2 register. It is cleared by a software se-

quence (an access to the SR register followed by a

read to the DR register).

0: No Idle Line is detected

1: Idle Line is detected

Note: The IDLE bit will not be set again until the

RDRF bit has been set itself (i.e. a new idle line oc-

curs). This bit is not set by an idle line when the re-

ceiver wakes up from wake-up mode.

Bit 3 = OR

Overrun error.

This bit is set by hardware when the word currently

being received in the shift register is ready to be

transferred into the RDR register while RDRF=1.

An interrupt is generated if RIE=1 in the CR2 reg-

ister. It is cleared by a software sequence (an ac-

cess to the SR register followed by a read to the

DR register).

0: No Overrun error

1: Overrun error is detected

Note: When this bit is set RDR register content will

not be lost but the shift register will be overwritten.

Bit 2 = NF

Noise flag.

This bit is set by hardware when noise is detected

on a received frame. It is cleared by a software se-

quence (an access to the SR register followed by a

read to the DR register).

0: No noise is detected

1: Noise is detected

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt.

Bit 1 = FE

Framing error.

This bit is set by hardware when a de-synchroniza-

tion, excessive noise or a break character is de-

tected. It is cleared by a software sequence (an

access to the SR register followed by a read to the

DR register).

0: No Framing error is detected

1: Framing error or break character is detected

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt. If the word currently

being transferred causes both frame error and

overrun error, it will be transferred and only the OR

bit will be set.

Bit 0 = Unused.

TDRE

RDRF

IDLE

ST72E331 数据表(PDF) 66 Page - STMicroelectronics

ST72E331 数据表(HTML) 66 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ST72E331 数据表(PDF) 66 Page - STMicroelectronics

ST72E331 数据表(HTML) 66 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载