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ST72E331 数据表(PDF) 69 Page - STMicroelectronics |
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ST72E331 数据表(HTML) 69 Page - STMicroelectronics |
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69 / 107 page  69/107 ST72E331 ST72T331 SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00 h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres- caler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 3.) is divided by the binary factor set in the ERPR register (in the range 1 to 255). The extended baud rate generator is not used af- ter a reset. EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (ETPR) Read/Write Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate divi- sion factor for the transmit circuit. Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres- caler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 3.) is divided by the binary factor set in the ETPR register (in the range 1 to 255). The extended baud rate generator is not used af- ter a reset. Table 17. SCI Register Map and Reset Values 70 ERPR 7 ERPR 6 ERPR 5 ERPR 4 ERPR 3 ERPR 2 ERPR 1 ERPR 0 70 ETPR 7 ETPR 6 ETPR 5 ETPR 4 ETPR 3 ETPR 2 ETPR 1 ETPR 0 Address (Hex.) Register Name 7 6 5 432 10 50 SR Reset Value TDRE 1 TC 1 RDRF 0 IDLE 0 OR 0 NF 0 FE 0 - 0 51 DR Reset Value DR7 - DR6 - DR5 - DR4 - DR3 - DR2 - DR1 - DR0 - 52 BRR Reset Value SCP1 0 SCP0 0 SCT2 - SCT1 - SCT0 - SCR2 - SCR1 - SCR0 - 53 CR1 Reset Value R8 - T8 -- M - WAKE -- -- 54 CR2 Reset Value TIE 0 TCIE 0 RIE 0 ILIE 0 TE 0 RE 0 RWU 0 SBK 0 55 ERPR Reset Value ERPR7 0 ERPR6 0 ERPR5 0 ERPR4 0 ERPR3 0 ERPR2 0 ERPR1 0 ERPR0 0 57 ETPR Reset Value ETPR7 0 ETPR6 0 ETPR5 0 ETPR4 0 ETPR3 0 ETPR2 0 ETPR1 0 ETPR0 0 69 |
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