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ST72E331 数据表(PDF) 96 Page - STMicroelectronics |
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ST72E331 数据表(HTML) 96 Page - STMicroelectronics |
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96 / 107 page  96/107 ST72E331 ST72T331 7.6 PERIPHERAL CHARACTERISTICS Notes: 1. The safe reset cannot be guaranted by the LVD when fosc is greater than 8MHz. 2. Based on characterisation results, not tested. Note 1: Based on characterisation results, not tested Low Voltage Detection Reset Electrical Specifications (Option) Symbol Parameter Conditions Min. Typ. Max. Unit VLVDUP LVD Reset Trigger, VDD rising edge fOSC = 8 MHz max 1). 3.6 2) 3.85 4.1 V VLVDDOWN LVD Reset Trigger, VDD falling edge 3.35 3.6 3.85 V VLVDHYS LVD Reset Trigger, hysteresis2) 250 mV EEPROM Specifications Parameter Conditions Min Max Unit Write Time TA ≤ 25°C; 3.5V to 5.5V @ fOSC = 16 MHz, 3V to 5.5V @ fOSC = 8 MHz 101) ms TA ≤ 85°C; 3.5V to 5.5V @ fOSC = 16 MHz, 3V to 5.5V @ fOSC = 8 MHz 15 TA ≤ 125°C; 3V to 5.5V @ fOSC = 8 MHz 20 Write Erase Cycles TA= 25°C 300,000 Cycles Data Retention TA= 55°C 10 Years 96 |
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