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ST72E331 数据表(PDF) 97 Page - STMicroelectronics |
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ST72E331 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 107 page  97/107 ST72E331 ST72T331 PERIPHERAL CHARACTERISTICS (Cont’d) (TA = -40°C to +125°C and VDD = 5V±10% unless otherwise specified ) *Note: ADC Accuracy vs. Negative Injection Current: For Iinj-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB by 10K Ω increase of the external analog source impedance. These measurements results and recommendations take worst case injection conditions into account: - negative injection - injection to an Input with analog capability, adjacent to the enabled Analog Input - at 5V VDD supply, and worst case temperature. A/D Converter Specifications Symbol Parameter Conditions Min Typ Max Unit TSAMPLE Sample Duration 31.5 1/fCPU Res ADC Resolution fCPU=8MHz VDD=VDDA=5V 8 bit DLE Differential Linearity Error* ±0.6 ±1 ILE Integral Linearity Error* ±2 VAIN Analog Input Voltage VSSA VDDA V IADC Supply current rise during A/D conversion fCPU=8MHz VDD=VDDA=5V 1mA tSTAB Stabilization time after ADC enable 30 µs tCONV Conversion Time 8 64 µs 1/fCPU RAIN Resistance of analog sources (VAIN) fCPU=8MHz, T=25°C, VDD=VDDA=5V 15 K Ω CHOLD Hold Capacitance 22 pF RSS Resistance of sampling switch and internal trace 2K Ω Px.x/AINx RAIN VAIN Cpin 5pF VDD VT = 0.6V leakage max. VT = 0.6V Cpin VT leakage Chold SS Sampling Switch SS RSS at the pin due to various junctions Chold 22 pF capacitance = input capacitance = threshold voltage = sampling switch = sample/hold ±1µA VSS = leakage current 2K Ω 97 |
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