ST72E331 datasheet(20/107 Pages) STMICROELECTRONICS

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ST72E331 ST72T331

RESET (Cont’d)

3.2.4 Low Voltage Detector Reset

The on-chip Low Voltage Detector (LVD) gener-

ates a static reset when the supply voltage is be-

low a reference value. The LVD functions both

during power-on as well as when the power supply

drops (brown-out). The reference value for a volt-

age drop is lower than the reference value for pow-

er-on in order to avoid a parasitic reset when the

MCU starts running and sinks current on the sup-

ply (hysteresis).

The LVD Reset circuitry generates a reset when

VDD is below:

VLVDUP when VDD is rising

VLVDDOWN when VDD is falling

Provided the minimun VDD value (guaranteed for

the oscillator frequency) is above VLVDDOWN , the

MCU can only be in two modes:

- under full software control or

- in static safe reset

In this condition, secure operation is always en-

sured for the application without the need for ex-

ternal reset hardware.

During a Low Voltage Detector Reset, the RESET

pin is held low, thus permitting the MCU to reset

other devices.

In noisy environments, the power supply may drop

for short periods and cause the Low Voltage De-

tector to generate a Reset too frequently. In such

cases, it is recommended to use devices without

the LVD Reset option and to rely on the watchdog

function to detect application runaway conditions.

Figure 14. Low Voltage Detector Reset Function

Figure 15. Low Voltage Detector Reset Signal

Note: See electrical characteristics for values of

VLVDUP and VLVDDOWN

Figure 16. Temporization timing diagram after an internal Reset

LOW VOLTAGE

DETECTOR RESET

VDD

FROM

WATCHDOG

RESET

VDD

VLVDUP

VLVDDOWN

VDD

Addresses

$FFFE

Temporization (4096 CPU clock cycles)

VLVDUP

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