ST72E331 datasheet(27/107 Pages) STMICROELECTRONICS

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ST72E331 ST72T331

5 ON-CHIP PERIPHERALS

5.1 I/O PORTS

5.1.1 Introduction

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs

and for specific pins:

– analog signal input (ADC)

– alternate signal input/output for the on-chip pe-

ripherals.

– external interrupt generation

An I/O port is composed of up to 8 pins. Each pin

can be programmed independently as digital input

(with or without interrupt generation) or digital out-

put.

5.1.2 Functional Description

Each port is associated to 2 main registers:

– Data Register (DR)

– Data Direction Register (DDR)

and some of them to an optional register:

– Option Register (OR)

Each I/O pin may be programmed using the corre-

sponding register bits in DDR and OR registers: bit

X corresponding to pin X of the port. The same cor-

respondence is used for the DR register.

The following description takes into account the

OR register, for specific ports which do not provide

this register refer to the I/O Port Implementation

Section 4.1.3. The generic I/O block diagram is

shown on Figure 21.

5.1.2.1 Input Modes

The input configuration is selected by clearing the

corresponding DDR register bit.

In this case, reading the DR register returns the

digital value applied to the external I/O pin.

Different input modes can be selected by software

through the OR register.

Notes:

1. All the inputs are triggered by a Schmitt trigger.

2. When switching from input mode to output

mode, the DR register should be written first to

output the correct value as soon as the port is con-

figured as an output.

Interrupt function

When an I/O is configured in Input with Interrupt,

an event on this I/O can generate an external In-

terrupt request to the CPU. The interrupt polarity is

given independently according to the description

mentioned in the Miscellaneous register or in the

interrupt register (where available).

Each pin can independently generate an Interrupt

request.

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see Interrupts sec-

tion). If several input pins are configured as inputs

to the same interrupt vector, their signals are logi-

cally ANDed before entering the edge/level detec-

tion block. For this reason if one of the interrupt

pins is tied low, it masks the other ones.

5.1.2.2 Output Mode

The pin is configured in output mode by setting the

corresponding DDR register bit.

In this mode, writing “0” or “1” to the DR register

applies this digital value to the I/O pin through the

latch. Then reading the DR register returns the

previously stored value.

Note: In this mode, the interrupt function is disa-

bled.

5.1.2.3 Digital Alternate Function

When an on-chip peripheral is configured to use a

pin, the alternate function is automatically select-

ed. This alternate function takes priority over

standard I/O programming. When the signal is

coming from an on-chip peripheral, the I/O pin is

automatically configured in output mode (push-pull

or open drain according to the peripheral).

When the signal is going to an on-chip peripheral,

the I/O pin has to be configured in input mode. In

this case, the pin’s state is also digitally readable

by addressing the DR register.

Notes:

1. Input pull-up configuration can cause an unex-

pected value at the input of the alternate peripher-

al input.

2. When the on-chip peripheral uses a pin as input

and output, this pin must be configured as an input

(DDR = 0).

Warning: The alternate function must not be acti-

vated as long as the pin is configured as input with

interrupt, in order to avoid generating spurious in-

terrupts.

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