ST72E331 datasheet(70/107 Pages) STMICROELECTRONICS

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ST72E331 ST72T331

5.6 SERIAL PERIPHERAL INTERFACE (SPI)

5.6.1 Introduction

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master and one or more slaves or a system in

which devices may be either masters or slaves.

The SPI is normally used for communication be-

tween the microcontroller and external peripherals

or another microcontroller.

Refer to the Pin Description chapter for the device-

specific pin-out.

5.6.2 Main Features

Full duplex, three-wire synchronous transfers

Master or slave operation

Four master mode frequencies

Maximum slave mode frequency = fCPU/2.

Four programmable master bit rates

Programmable clock polarity and phase

End of transfer interrupt flag

Write collision flag protection

Master mode fault protection capability.

5.6.3 General description

The SPI is connected to external devices through

4 alternate pins:

– MISO: Master In Slave Out pin

– MOSI: Master Out Slave In pin

– SCK: Serial Clock pin

–SS: Slave select pin

A basic example of interconnections between a

single master and a single slave is illustrated on

Figure 1.

The MOSI pins are connected together as are

MISO pins. In this way data is transferred serially

between master and slave (most significant bit

first).

When the master device transmits data to a slave

device via MOSI pin, the slave device responds by

sending data to the master device via the MISO

pin. This implies full duplex transmission with both

data out and data in synchronized with the same

clock signal (which is provided by the master de-

vice via the SCK pin).

Thus, the byte transmitted is replaced by the byte

received and eliminates the need for separate

transmit-empty and receiver-full bits. A status flag

is used to indicate that the I/O operation is com-

plete.

Four possible data/clock timing relationships may

be chosen (see Figure 4) but master and slave

must be programmed with the same timing mode.

Figure 40. Serial Peripheral Interface Master/Slave

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

8-BIT SHIFT REGISTER

MISO

MOSI

MISO

SCK

SLAVE

MASTER

+5V

MSBit

LSBit

MSBit

LSBit

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