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ST72E331 数据表(PDF) 75 Page - STMicroelectronics |
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ST72E331 数据表(HTML) 75 Page - STMicroelectronics |
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75 / 107 page ![]() 75/107 ST72E331 ST72T331 SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 43. Data Clock Timing Diagram CPOL = 1) CPOL = 0) MISO (from master) MOSI (from slave) SS (to slave) CAPTURE STROBE CPHA =1 CPOL = 1 CPOL = 0 MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MISO (from master) MOSI SS (to slave) CAPTURE STROBE CPHA =0 Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter. (from slave) VR02131B MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit SCLK (with SCLK (with 75 |
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