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ST72E331 数据表(PDF) 13 Page - STMicroelectronics |
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ST72E331 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 107 page  13/107 ST72E331 ST72T331 Notes: 1. The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value. 2. External pin not available. 3. Not used in versions without Low Voltage Detector Reset. 0031h 0032h 0033h 0034h-0035h 0036h-0037h 0038h-0039h 003Ah-003Bh 003Ch-003Dh 003Eh-003Fh Timer A TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only2) Read Only2) R/W2) R/W2) 0040h Reserved Area (1 byte) 0041h 0042h 0043h 0044h-0045h 0046h-0047h 0048h-0049h 004Ah-004Bh 004Ch-004Dh 004Eh-004Fh Timer B TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h SCI SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved SCI Extended Transmit Prescaler Register C0h xxh 00x----xb xxh 00h 00h --- 00h Read Only R/W R/W R/W R/W R/W Reserved R/W 0058h to 006Fh Reserved Area (24 bytes) 0070h 0071h ADC ADCDR ADCCSR ADC Data Register ADC Control/Status Register 00h 00h Read Only R/W 0072h to 007Fh Reserved Area (14 bytes) Address Block Register Label Register Name Reset Status Remarks 13 |
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