ST72E331 datasheet(74/107 Pages) STMICROELECTRONICS

74 / 107 page

74/107

ST72E331 ST72T331

SERIAL PERIPHERAL INTERFACE (Cont’d)

5.6.4.3 Data Transfer Format

During an SPI transfer, data is simultaneously

transmitted (shifted out serially) and received

(shifted in serially). The serial clock is used to syn-

chronize the data transfer during a sequence of

eight clock pulses.

The SS pin allows individual selection of a slave

device; the other slave devices that are not select-

ed do not interfere with the SPI transfer.

Clock Phase and Clock Polarity

Four possible timing relationships may be chosen

by software, using the CPOL and CPHA bits.

The CPOL (clock polarity) bit controls the steady

state value of the clock when no data is being

transferred. This bit affects both master and slave

modes.

The combination between the CPOL and CPHA

(clock phase) bits selects the data capture clock

edge.

Figure 4, shows an SPI transfer with the four com-

binations of the CPHA and CPOL bits. The dia-

gram may be interpreted as a master or slave tim-

ing diagram where the SCK pin, the MISO pin, the

MOSI pin are directly connected between the mas-

ter and the slave device.

The SS pin is the slave device select input and can

be driven by the master device.

The master device applies data to its MOSI pin-

clock edge before the capture clock edge.

CPHA bit is set

The second edge on the SCK pin (falling edge if

the CPOL bit is reset, rising edge if the CPOL bit is

set) is the MSBit capture strobe. Data is latched on

the occurrence of the second clock transition.

No write collision should occur even if the SS pin

stays low during a transfer of several bytes (see

Figure 3).

CPHA bit is reset

The first edge on the SCK pin (falling edge if CPOL

bit is set, rising edge if CPOL bit is reset) is the

MSBit capture strobe. Data is latched on the oc-

currence of the first clock transition.

The SS pin must be toggled high and low between

each byte transmitted (see Figure 3).

To protect the transmission from a write collision a

low value on the SS pin of a slave device freezes

the data in its DR register and does not allow it to

be altered. Therefore the SS pin must be high to

write a new data byte in the DR without producing

a write collision.

Figure 42. CPHA / SS Timing Diagram

MOSI/MISO

Master

Slave

(CPHA=0)

Slave

(CPHA=1)

Byte 1

Byte 2

Byte 3

VR02131A

ST72E331 数据表(PDF) 74 Page - STMicroelectronics

ST72E331 数据表(HTML) 74 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载