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M306V2EEFS 数据表(PDF) 34 Page - Renesas Technology Corp |
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M306V2EEFS 数据表(HTML) 34 Page - Renesas Technology Corp |
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34 / 271 page  Rev.1.40 Oct 06, 2004 page 34 of 269 M306V2ME-XXXFP, M306V2EEFP (9) Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516) (Note) and bits 4 to 7 of the chip select control register (address 000816). A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcom- puter has been reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two or three BCLK cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring to the recommended operating conditions (main clock input oscillation fre- ________ quency) of the electric characteristics. However, when the user is using the RDY signal, the relevant bit in the chip select control register’s bits 4 to 7 must be set to “0.” When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register _______ _______ correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits default to “0” after the microcomputer has been reset. These bits default to “0” after the microcomputer has been reset. The SFR area and the OSD RAM area are always accessed in two BCLK cycles regardless of the setting of these control bits. Also, the corresponding bits of the chip select control register must be set to “0” if using the multiplex bus to access the external memory area. Table 2.4.9 shows the software wait and bus cycles. Figure 2.4.8 shows example bus timing when using software waits. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A16) to “1”. Table 2.4.9 Software waits and bus cycles |
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