M306V2EEFS datasheet(69/271 Pages) RENESAS

69 / 271 page

Rev.1.40

Oct 06, 2004 page 69 of 269

M306V2ME-XXXFP, M306V2EEFP

2.9 DMAC

This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to

memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a

higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this

account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-

bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 2.9.1 shows the block diagram of

the DMAC. Table 2.9.1 shows the DMAC specifications. Figures 2.9.2 to 2.9.7 show the registers used by

the DMAC.

Figure 2.9.1 Block diagram of DMAC

Data bus low-order bits

DMA latch high-order bitsDMA latch low-order bits

DMA0 source pointer SAR0(20)

DMA0 destination pointer DAR0 (20)

DMA0 forward address pointer (20) (Note)

Data bus high-order bits

Address bus

DMA1 destination pointer DAR1 (20)

DMA1 source pointer SAR1 (20)

DMA1 forward address pointer (20) (Note)

DMA0 transfer counter reload register TCR0 (16)

DMA0 transfer counter TCR0 (16)

DMA1 transfer counter reload register TCR1 (16)

DMA1 transfer counter TCR1 (16)

(addresses 0029 16, 002816)

(addresses 0039 16, 003816)

(addresses 0022 16 to 002016)

(addresses 0026 16 to 002416)

(addresses 0032 16 to 003016)

(addresses 0036 16 to 003416)

Note: Pointer is incremented by a DMA request.

Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer

request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the

interrupt priority level. The DMA transfer doesn't affect any interrupts either.

If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request

signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA

transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the

number of transfers. For details, see the description of the DMA request bit.

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