M306V2EEFS datasheet(32/271 Pages) RENESAS

32 / 271 page

Rev.1.40

Oct 06, 2004 page 32 of 269

M306V2ME-XXXFP, M306V2EEFP

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(5) RDY signal

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RDY signal facilitates access of external devices that require a long time for access. As shown in

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Figure 2.4.6, if an “L” is being input to the RDY pin at the BCLK falling edge, the bus turns to the wait

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state. If an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state.

Table 2.4.6 shows the microcomputer state in the wait state. Figure 2.4.6 shows the example of the

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RD signal being extended using the RDY signal.

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The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of

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the chip select control register (address 000816) are set to “0.” The RDY signal is invalid when setting

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“1” to all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be

treated as properly as in non-using.

Table 2.4.6 Microcomputer status in ready state (Note)

Item

Status

Oscillation

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_____

R/W signal, address bus, data bus, CS

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Maintain status when RDY signal received

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ALE signal, HLDA, programmable I/O ports

Internal peripheral circuitsOn

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Note: The RDY signal cannot be received immediately prior to a software wait.

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Figure 2.4.6 Example of RD signal extended by RDY signal

BCLK

CSi

(i=0 to 3)

RDY

tsu(RDY - BCLK)

BCLK

CSi

(i=0 to 3)

RDY

tsu(RDY - BCLK)

In an instance of separate bus

In an instance of multiplexed bus

Accept timing of RDY signal

: Wait using RDY signal

: Wait using software

Accept timing of RDY signal

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