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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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M306V2EEFS 数据表(PDF) 44 Page - Renesas Technology Corp |
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M306V2EEFS 数据表(HTML) 44 Page - Renesas Technology Corp |
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44 / 271 page  Rev.1.40 Oct 06, 2004 page 44 of 269 M306V2ME-XXXFP, M306V2EEFP 2.5.8 Power Control The following is a description of the three available power control modes: Modes Power control is available in three modes. (1) Normal operation mode ■ High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock. ■ Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock. ■ Low-speed mode fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock. ■ Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (2) Wait mode The CPU operation is stopped. The oscillators do not stop. (3) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 2.5.7 is the state transition diagram of the above modes. |
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