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M306V2EEFS 数据表(PDF) 75 Page - Renesas Technology Corp

部件名 M306V2EEFS
功能描述  SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PDF  271 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

M306V2EEFS 数据表(HTML) 75 Page - Renesas Technology Corp

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Rev.1.40
Oct 06, 2004 page 75 of 269
M306V2ME-XXXFP, M306V2EEFP
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
CPU use
CPU use
Source
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(1) 8-bit transfers
16-bit transfers from even address and the source address is even.
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
CPU use
CPU use
Source
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
CPU use
CPU use
Source
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles).
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
CPU use
CPU use
Source
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles).
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 2.9.8 Example of the transfer cycles for a source read



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