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M306V2EEFS 数据表(PDF) 62 Page - Renesas Technology Corp |
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M306V2EEFS 数据表(HTML) 62 Page - Renesas Technology Corp |
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62 / 271 page  Rev.1.40 Oct 06, 2004 page 62 of 269 M306V2ME-XXXFP, M306V2EEFP Figure 2.7.8 Hardware interrupts priorities ________ Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match Figure 2.7.9 Maskable interrupts priorities (peripheral I/O interrupts) VSYNC UART0 reception UART2 reception A-D conversion DMA1 Bus collision detection Timer A0 Data slicer UART0 transmission UART2 transmission Priority of peripheral I/O interrupts (if priority levels are same) OSD2 Timer B2 Timer B0 Timer A3 Timer A1 Timer B1 Timer A4 Timer A2 INT1 INT0 Level 0 (initial value) Priority level of each interrupt High OSD1 Low DMA0 Interrupt enable flag (I flag) Watchdog timer Reset DBC Interrupt request accepted Address match Processor interrupt priority level (IPL) Multi-master I2C-BUS interface 0 Multi-master I2C-BUS interface 1 |
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