M306V2EEFS datasheet(78/271 Pages) RENESAS

78 / 271 page

Rev.1.40

Oct 06, 2004 page 78 of 269

M306V2ME-XXXFP, M306V2EEFP

The timing for the DMA request bit to turn to 1 when an external factor is selected synchronizes with

the signal’s edge applicable to the function specified by the DMA request factor selection bit (synchro-

_______

nizes with the trailing edge of the input signal to each INTi pin, for example).

With an external factor selected, the DMA request bit is timed to turn to 0 immediately before data

transfer starts similarly to the state in which an internal factor is selected.

(3) The priorities of channels and DMA transfer timing

If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period

from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels

concurrently turn to 1. If the channels are active at that moment, DMA0 is given a high priority to start

data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU

finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. Figure

2.9.9 illustrates these operations.

An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer

request signals due to external factors concurrently occur.

BCLK

DMA0

DMA1

DMA0

request bit

DMA1

request bit

CPU

INT0

INT1

Obtainm

ent of the

bus right

An example in which DMA transmission is carried out in minimum

cycles at the time when DMA transmission request signals due to

external factors concurrently occur.

Figure 2.9.9 An example of DMA transfer effected by external factors

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