M306V2EEFS datasheet(40/271 Pages) RENESAS

40 / 271 page

Rev.1.40

Oct 06, 2004 page 40 of 269

M306V2ME-XXXFP, M306V2EEFP

Figures 2.5.5 and 2.5.6 shows the system clock control registers 0 and 1.

Figure 2.5.6 System clock control register 1

System clock control register 1 (Note 1)

Symbol

Address

When reset

CM1

000716

2016

Bit name

Function

Bit symbol

b7b6b5b4b3b2b1b0

CM10

All clock stop control bit

(Note 4)

0 : Clock on

1 : All clocks off (stop mode)

Notes 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.

2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a

reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop

mode is retained.

3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0.”

If “1”, division mode is fixed at 8.

4: If this bit is set to “1,” XOUT turns “H,” and the built-in feedback resistor is cut off. XCIN and XCOUT turn

high-impedance state.

CM15

XIN-XOUT drive capacity

select bit (Note 2)

0 : LOW

1 : HIGH

CM16

CM17

Main clock division

select bit 1 (Note 3)

0 0 : No division mode

0 1 : Division by 2 mode

1 0 : Division by 4 mode

1 1 : Division by 16 mode

b7 b6

Reserved bits

Must always be set to

“0”

Figures 2.5.5 System clock control register 0

System clock control register 0 (Note 1)

Symbol

Address

When reset

CM0

000616

4816

Bit name

Function

Bit symbol

0 0 : I/O port P57

0 1 : fC output

1 0 : f8 output

1 1 : f32 output

b1 b0

CM07

CM05

CM04

CM03

CM01

CM02

CM00

CM06

Clock output function

select bit

(Valid only in single-chip

mode)

WAIT peripheral function

clock stop bit

0 : Do not stop peripheral function clock in wait mode

1 : Stop peripheral function clock in wait mode (Note 8)

XCIN-XCOUT drive capacity

select bit (Note 2)

0 : LOW

1 : HIGH

Port XC select bit

0 : I/O port

1 : XCIN-XCOUT generation

Main clock (XIN-XOUT)

stop bit (Notes 3, 4, 5)

0 : On

1 : Off

Main clock division select

bit 0 (Note 7)

0 : CM16 and CM17 valid

1 : Division by 8 mode

System clock select bit

(Note 6)

0 : XIN, XOUT

1 : XCIN, XCOUT

Notes 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.

2: Changes to “1” when shifting to stop mode and at a reset.

3: When entering power saving mode, main clock stops using this . When returning from stop mode and

operating with XIN, set this bit to “0.” When main clock oscillation is operating by itself, set system clock select

bit (CM07) to “1” before setting this bit to “1”.

4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.

5: If this bit is set to “1,” XOUT turns “H.” The built-in feedback resistor remains being connected, so XIN turns

pulled up to XOUT (“H”) via the feedback resistor.

6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to

“1.” Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize

the main clock oscillating before setting this bit from “1” to “0.”

7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When

shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

8: fC32 is not included.

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