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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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M306V2EEFS 数据表(PDF) 38 Page - Renesas Technology Corp |
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M306V2EEFS 数据表(HTML) 38 Page - Renesas Technology Corp |
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38 / 271 page  Rev.1.40 Oct 06, 2004 page 38 of 269 M306V2ME-XXXFP, M306V2EEFP 2.5.3 Clock Control Figure 2.5.4 shows the block diagram of the clock generating circuit. Sub clock CM04 fC32 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16 XCIN CM10 “1” Write signal 1/32 XCOUT Q S R WAIT instruction XOUT Main clock CM05 fC CM02 f1 Q S R Interrupt request level judgment output RESET Software reset fC CM07=0 CM07=1 fAD Divider a d 1/2 1/2 1/2 1/2 CM06=0 CM17,CM16=00 CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=10 CM06=1 CM06=0 CM17,CM16=11 d a Details of divider XIN f8 f32 c b b 1/2 c f32SIO2 f8SIO2 f1SIO2 BCLK Figure 2.5.4 Clock generating circuit 2.5.2 OSD Oscillation Circuit The OSD clock oscillation circuit can obtain simply a clock for OSD by connecting an LC oscillator or a ceramic resonator (or a quartz-crystal oscillator) across the pins OSC1 and OSC2. Which of LC oscillator or a ceramic resonator (or a quartz-crystal oscillator) is selected by setting bits 1 and 2 of the clock control register (address 020516). Figure 2.5.3 OSD clock connection example OSC2 OSC1 L C1 C2 Microcomputer |
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