H8SSLASH2218 datasheet(34/750 Pages) RENESAS

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Rev.6.00 Jun. 03, 2008 Page xxxii of xlvi

REJ09B0074-0600

Section 9 16-Bit Timer Pulse Unit (TPU)

Figure 9.1

Block Diagram of TPU ...........................................................................................274

Figure 9.2

16-Bit Register Access Operation [Bus Master

↔ TCNT (16 Bits)] .....................299

Figure 9.3

8-Bit Register Access Operation [Bus Master

↔ TCR (Upper 8 Bits)] .................300

Figure 9.4

8-Bit Register Access Operation [Bus Master

↔ TMDR (Lower 8 Bits)].............300

Figure 9.5

8-Bit Register Access Operation [Bus Master

↔ TCR and TMDR (16 Bits)].......300

Figure 9.6

Example of Counter Operation Setting Procedure..................................................301

Figure 9.7

Free-Running Counter Operation ...........................................................................302

Figure 9.8

Periodic Counter Operation ....................................................................................303

Figure 9.9

Example of Setting Procedure for Waveform Output by Compare Match .............303

Figure 9.10 Example of 0 Output/1 Output Operation...............................................................304

Figure 9.11 Example of Toggle Output Operation.....................................................................304

Figure 9.12 Example of Input Capture Operation Setting Procedure.........................................305

Figure 9.13 Example of Input Capture Operation ......................................................................306

Figure 9.14 Example of Synchronous Operation Setting Procedure..........................................307

Figure 9.15 Example of Synchronous Operation .......................................................................308

Figure 9.16 Compare Match Buffer Operation ..........................................................................309

Figure 9.17 Input Capture Buffer Operation ..............................................................................309

Figure 9.18 Example of Buffer Operation Setting Procedure ....................................................310

Figure 9.19 Example of Buffer Operation (1)............................................................................311

Figure 9.20 Example of Buffer Operation (2)............................................................................312

Figure 9.21 Example of PWM Mode Setting Procedure............................................................314

Figure 9.22 Example of PWM Mode Operation (1) ..................................................................315

Figure 9.23 Example of PWM Mode Operation (2) ..................................................................315

Figure 9.24 Example of PWM Mode Operation (3) ..................................................................316

Figure 9.25 Example of Phase Counting Mode Setting Procedure ............................................317

Figure 9.26 Example of Phase Counting Mode 1 Operation......................................................318

Figure 9.27 Example of Phase Counting Mode 2 Operation......................................................319

Figure 9.28 Example of Phase Counting Mode 3 Operation......................................................320

Figure 9.29 Example of Phase Counting Mode 4 Operation......................................................321

Figure 9.30 Count Timing in Internal Clock Operation .............................................................324

Figure 9.31 Count Timing in External Clock Operation ............................................................324

Figure 9.32 Output Compare Output Timing .............................................................................325

Figure 9.33 Input Capture Input Signal Timing .........................................................................325

Figure 9.34 Counter Clear Timing (Compare Match)................................................................326

Figure 9.35 Counter Clear Timing (Input Capture) ...................................................................326

Figure 9.36 Buffer Operation Timing (Compare Match) ...........................................................327

Figure 9.37 Buffer Operation Timing (Input Capture)...............................................................327

Figure 9.38 TGI Interrupt Timing (Compare Match).................................................................328

Figure 9.39 TGI Interrupt Timing (Input Capture) ....................................................................328

Figure 9.40 TCIV Interrupt Setting Timing ...............................................................................329

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