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H8S/2218 数据表(PDF) 12 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 12 Page - Renesas Technology Corp |
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12 / 750 page  Rev.6.00 Jun. 03, 2008 Page xii of xlviii REJ09B0074-0600 Item Page Revision (See Manual for Details) 22.2 Power Supply Voltage and Operating Frequency Range Figure 22.1 Power Supply Voltage and Operating Ranges 658 Figure replaced 22.3 DC Characteristics 659 Condition D added Condition D: VCC = PLL VCC = Dr VCC = 3.0 V to 3.6 V, Vref = 3.0 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 16 MHz to 24 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Table 22.3 Permissible Output Currents 662 Condition D added Condition D: VCC = PLL VCC = Dr VCC = 3.0 V to 3.6 V, Vref = 3.0 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 16 MHz to 24 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) 22.4.1 Clock Timing Table 22.4 Clock Timing 664 Condition D added Condition D: VCC = PLL VCC = Dr VCC = 3.0 V to 3.6 V, Vref = 3.0 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 16 MHz to 24 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) 664 - 665 Table amended Item Unit Symbol Min. Max. Condition A Min. Max. Condition B Min. Max. Condition C Min. Max. Test Conditions Condition D Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Oscillation stabilization time at reset (crystal) Oscillation stabilization time in software standby (crystal) External clock output stabilization delay time Subclock stabilization time Subclock oscillator frequency Subclock ( φSUB) cycle time 62.5 20 20 ⎯ ⎯ 20 8 8 500 ⎯ 166.6 ⎯ ⎯ 10 10 ⎯ ⎯ ⎯ ⎯ 2 41.6 13 13 ⎯ ⎯ 20 8 4 500 ⎯ 166.6 ⎯ ⎯ 7 7 ⎯ ⎯ ⎯ ⎯ 2 41.6 13 13 ⎯ ⎯ 20 8 4 500 ⎯ 62.5 ⎯ ⎯ 7 7 ⎯ ⎯ ⎯ ⎯ 2 ns ns ns ns ns ms ms ms μs s kHz μs Figure 22.3 Figure 22.4 Figures 20.4, 19.2 CL1 = CL2 = 10 to 22 pF Figures 20.4, 19.2 CL1 = CL2 = 10 to 15 pF Figure 22.4 tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT tOSC3 fSUB fSUB 166.6 32.768 30.5 32.768 30.5 32.768 30.5 32.768 30.5 50 50 ⎯ ⎯ 40 16 16 1000 ⎯ ⎯ ⎯ 25 25 ⎯ ⎯ ⎯ ⎯ 4 |
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