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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2218 数据表(PDF) 89 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 89 Page - Renesas Technology Corp |
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89 / 750 page  Section 2 CPU Rev.6.00 Jun. 03, 2008 Page 41 of 698 REJ09B0074-0600 SP (ER7) Free area Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is two bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions. When these instructions except for the STC instruction is executed, all interrupts including NMI will be masked for three states after execution is completed. Bit Bit Name Initial Value R/W Description 7 T 0 R/W Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 – All 1 – Reserved These bits are always read as 1. 2 1 0 I2 I1 I0 1 R/W These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. |
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