H8SSLASH2218 datasheet(27/750 Pages) RENESAS

27 / 750 page

Rev.6.00 Jun. 03, 2008 Page xxv of xlvi

REJ09B0074-0600

17.8

Flash Memory Programming/Erasing ............................................................................... 579

17.8.1 Program/Program-Verify ..................................................................................... 579

17.8.2 Erase/Erase-Verify ............................................................................................... 581

17.9

Program/Erase Protection.................................................................................................. 583

17.9.1 Hardware Protection ............................................................................................ 583

17.9.2 Software Protection.............................................................................................. 583

17.9.3 Error Protection.................................................................................................... 583

17.10 Interrupt Handling when Programming/Erasing Flash Memory ....................................... 584

17.11 Programmer Mode ............................................................................................................ 585

17.12 Power-Down States for Flash Memory ............................................................................. 586

17.13 Flash Memory Programming and Erasing Precautions ..................................................... 587

17.14 Note on Switching from F-ZTAT Version to Masked ROM Version .............................. 592

Section 18 Masked ROM ..................................................................................................593

18.1

Features ............................................................................................................................. 593

Section 19 Clock Pulse Generator ..................................................................................595

19.1

Register Descriptions ........................................................................................................ 596

19.1.1 System Clock Control Register (SCKCR) ........................................................... 596

19.1.2 Low Power Control Register (LPWRCR)............................................................ 597

19.2

System Clock Oscillator.................................................................................................... 600

19.2.1 Connecting a Crystal Resonator........................................................................... 600

19.2.2 Inputting External Clock ...................................................................................... 601

19.3

Duty Adjustment Circuit ................................................................................................... 602

19.4

Medium-Speed Clock Divider .......................................................................................... 602

19.5

Bus Master Clock Selection Circuit .................................................................................. 602

19.6

Subclock Oscillator ........................................................................................................... 603

19.6.1 Connecting 32.768-kHz Crystal Resonator.......................................................... 603

19.6.2 Handling Pins when Subclock Not Required ....................................................... 603

19.7

Subclock Waveform Generation Circuit ........................................................................... 604

19.8

PLL Circuit for USB ......................................................................................................... 604

19.9

Usage Notes ...................................................................................................................... 605

19.9.1 Note on Crystal Resonator ................................................................................... 605

19.9.2 Note on Board Design.......................................................................................... 605

19.9.3 Note on Switchover of External Clock ................................................................ 605

Section 20 Power-Down Modes......................................................................................607

20.1

Register Descriptions ........................................................................................................ 611

20.1.1 Standby Control Register (SBYCR) .................................................................... 611

20.1.2 Timer Control/Status Register (TCSR_1) ............................................................ 613

20.1.3 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)................... 614

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