H8SSLASH2218 datasheet(9/750 Pages) RENESAS

9 / 750 page

Rev.6.00 Jun. 03, 2008 Page ix of xlviii

REJ09B0074-0600

Item

Page

Revision (See Manual for Details)

12.7.7 Serial Data

Transmission (Except

for Block Transfer

Mode)

432

Description amended and added

Figure 12.31 shows a flowchart for transmission. A sequence of

transmit operations can be performed automatically by

specifying the DMAC to be activated with a TXI interrupt source.

In a transmit operation, the TDRE flag is set to 1 at the same

time as the TEND flag in SSR is set, and a TXI interrupt will be

generated if the TIE bit in SCR has been set to 1. If the TXI

request is designated beforehand as a DMAC activation source,

the DMAC will be activated by the TXI request, and transfer of

the transmit data will be carried out. The TDRE and TEND flags

are automatically cleared to 0 when data is transferred by the

DMAC. In the event of an error, the SCI retransmits the same

data automatically. During this period, the TEND flag remains

cleared to 0 and the DMAC is not activated. Therefore, the SCI

and DMAC will automatically transmit the specified number of

bytes in the event of an error, including retransmission.

However, the ERS flag is not cleared automatically when an

error occurs, and so the RIE bit should be set to 1 beforehand

so that an ERI request will be generated in the event of an error,

and the ERS flag will be cleared. When using the DMAC for

data transmission or reception, always make DMAC settings

and enable the DMAC before making SCI settings. For details

on DMAC settings, see section 7, DMA Controller (DMAC).

12.7.8 Serial Data

Reception (Except for

Block Transfer Mode)

435

Description amended

Figure 12.33 shows a flowchart for reception. A sequence of

receive operations can be performed automatically by

specifying the DMAC to be activated using an RXI interrupt

source. In a receive operation, an RXI interrupt request is

generated when the RDRF flag in SSR is set to 1. If the RXI

request is designated beforehand as a DMAC activation source,

the DMAC will be activated by the RXI request, and the receive

data will be transferred. The RDRF flag is cleared to 0

automatically when data is transferred by the DMAC. If an error

occurs in receive mode and the ORER or PER flag is set to 1, a

transfer error interrupt (ERI) request will be generated. Hence,

so the error flag must be cleared to 0. In the event of an error,

the DMAC is not activated and receive data is skipped.

Therefore, receive data is transferred for only the specified

number of bytes in the event of an error. Even when a parity

error occurs in receive mode and the PER flag is set to 1, the

data that has been received is transferred to RDR and can be

read from there.

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