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H8S/2218 数据表(PDF) 13 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 13 Page - Renesas Technology Corp |
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13 / 750 page  Rev.6.00 Jun. 03, 2008 Page xiii of xlviii REJ09B0074-0600 Item Page Revision (See Manual for Details) 22.4.2 Control Signal Timing Table 22.5 Control Signal Timing 666 Condition D added Condition D: VCC = PLL VCC = Dr VCC = 3.0 V to 3.6 V, Vref = 3.0 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 16 MHz to 24 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) 22.4.3 Bus Timing Table 22.6 Bus Timing 668 Condition D added Condition D: VCC = PLL VCC = Dr VCC = 3.0 V to 3.6 V, Vref = 3.0 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 16 MHz to 24 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) 22.4.4 Timing of On- Chip Supporting Modules Table 22.7 Timing of On-Chip Supporting Modules 675 Condition D added Condition D: VCC = PLL VCC = Dr VCC = 3.0 V to 3.6 V, Vref = 3.0 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 16 MHz to 24 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) 22.6 A/D Conversion Characteristics Table 22.9 A/D Conversion Characteristics 682 Condition D added Condition D: VCC = PLL VCC = Dr VCC = 3.0 V to 3.6 V, Vref = 3.0 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 16 MHz to 24 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) 682 Table amended Item Condition A Min. Typ. Condition B, C, D Max. Min. Typ. Max. Unit Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy 10 21.8 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 10 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 10 ⎯ 20 5 ±6.0 ±4.0 ±4.0 ±0.5 ±8.0 10 8.1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 10 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 10 ⎯ 20 5 ±6.0 ±4.0 ±4.0 ±0.5 ±6.0 bits μs pF k Ω LSB LSB LSB LSB LSB |
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