H8SSLASH2218 datasheet(11/750 Pages) RENESAS

11 / 750 page

Rev.6.00 Jun. 03, 2008 Page xi of xlviii

REJ09B0074-0600

Item

Page

Revision (See Manual for Details)

15.1 Features

535

Description amended

• Conversion time: 8.1 µs per channel (at 16-MHz operation),

10.7 µs per channel (at 24-MHz operation), 21.8 µs per

channel (at 6-MHz operation)

16 RAM

551

Description amended

…The H8S/2210 and H8S/2210S has 4 kbytes of on-chip high-

speed static RAM.

Table amended

Product Class

ROM Type

RAM Size

RAM Address

H8S/2212

Group

Masked ROM Version

4 kbytes

H'FFE000 to H'FFEFBF

H'FFFFC0 to H'FFFFFF

HD6432210

HD6432210S

17.4 Input/Output Pins

Table 17.2 Pin

Configuration

560

Table amended

Pin Name

I/O

Function

PF3, PF0, P16,

P14

Input

Sets this LSI's operating mode in programmer

mode

All

EMLE

Input

Emulator enable

TxD2

Output

Serial transmit data output

RxD2

Input

Serial receive data input

HD64F2218,

HD64F2212,

HD64F2211

18.1 Features

593

Table amended

Product Class

ROM Size

ROM Address (Modes 6 and 7)

H8S/2218 Group

H8S/2212 Group

64 kbytes

32 kbytes

H'000000 to H'00FFFF

H'000000 to H'007FFF

HD6432217

HD6432211

HD6432210, HD6432210S

19.8 PLL Circuit for

USB

604

Description amended

The PLL circuit has the function of doubling or tripling the 16-

MHz or 24-MHz clock from the main oscillator to generate the

48-MHz USB operating clock.

When the PLL circuit is used, set the UCKS3 to UCKS0 bits of

UCTLR. For details, refer to section 14, Universal Serial Bus

(USB).

When the PLL circuit is not used, connect the PLVCC pin to Vcc

and the PLLVSS pin to the ground (Vss). Figure 19.9 shows

examples of external circuits peripheral to the PLL.

Figure 19.9 Example

of PLL Circuit

Figure added

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