H8SSLASH2218 datasheet(95/750 Pages) RENESAS

95 / 750 page

Section 2 CPU

Rev.6.00 Jun. 03, 2008 Page 47 of 698

REJ09B0074-0600

2.6.1

Table of Instructions Classified by Function

Tables 2.3 to 2.10 summarizes the instructions in each functional category. The notation used in

tables 2.3 to 2.10 is defined below.

Table 2.2

Operation Notation

Symbol

Description

General register (destination)*

General register (source) *

General register*

ERn

General register (32-bit register)

(EAd)

Destination operand

(EAs)

Source operand

EXR

Extended control register

CCR

Condition-code register

N (negative) flag in CCR

Z (zero) flag in CCR

V (overflow) flag in CCR

C (carry) flag in CCR

Program counter

Stack pointer

#IMM

Immediate data

disp

Displacement

Addition

–

Subtraction

Multiplication

Division

∧

Logical AND

∨

Logical OR

⊕

Logical exclusive OR

→

Move

∼

NOT (logical complement)

:8/:16/:24/:32

8-, 16-, 24-, or 32-bit length

Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit registers (ER0 to ER7).

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