H8SSLASH2218 datasheet(98/750 Pages) RENESAS

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Section 2 CPU

Rev.6.00 Jun. 03, 2008 Page 50 of 698

REJ09B0074-0600

Instruction Size*

Function

NEG

B/W/L

0 – Rd

→ Rd

Takes the two's complement (arithmetic complement) of data in a

general register.

EXTU

W/L

Rd (zero extension)

→ Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16

bits of a 32-bit register to longword size, by padding with zeros on the

left.

EXTS

W/L

Rd (sign extension)

→ Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16

bits of a 32-bit register to longword size, by extending the sign bit.

TAS*

@ERd – 0, 1

→ (<bit 7> of @ERd)

Tests memory contents, and sets the most significant bit (bit 7) to 1.

Notes: 1. Size refers to the operand size.

B: Byte

W: Word

L: Longword

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

Table 2.5

Logic Operations Instructions

Instruction Size*

Function

AND

B/W/L

∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another

general register or immediate data.

B/W/L

∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another

general register or immediate data.

XOR

B/W/L

⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and

another general register or immediate data.

NOT

B/W/L

∼ Rd → Rd

Takes the one's complement (logical complement) of general register

contents.

Note: * Size refers to the operand size.

B: Byte

W: Word

L: Longword

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