H8SSLASH2218 datasheet(32/750 Pages) RENESAS

32 / 750 page

Rev.6.00 Jun. 03, 2008 Page xxx of xlvi

REJ09B0074-0600

Section 3 MCU Operating Modes

Figure 3.1

Memory Map in Each Operating Mode for HD64F2218 and HD64F2218U .........77

Figure 3.2

Memory Map in Each Operating Mode for HD6432217........................................78

Figure 3.3

Memory Map in Each Operating Mode for HD64F2212, HD64F2212U,

HD64F2211, HD64F2211U, HD6432211, HD6432210, HD6432210S and

HD6432210S ..........................................................................................................79

Section 4 Exception Handling

Figure 4.1

Reset Sequence (Mode 4) .......................................................................................85

Figure 4.2

Reset Sequence (Modes 6 and 7) ............................................................................86

Figure 4.3

Stack Status after Exception Handling ...................................................................89

Figure 4.4

Operation when SP Value Is Odd ...........................................................................90

Section 5 Interrupt Controller

Figure 5.1

Block Diagram of Interrupt Controller ...................................................................92

Figure 5.2

Block Diagram of Interrupts IRQn .........................................................................99

Figure 5.3

Timing of Setting IRQnF ........................................................................................100

Figure 5.4

Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control

Mode 0....................................................................................................................104

Figure 5.5

Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control

Mode 2....................................................................................................................106

Figure 5.6

Interrupt Exception Handling .................................................................................107

Figure 5.7

Interrupt Control for DMAC...................................................................................110

Figure 5.8

Contention between Interrupt Generation and Disabling........................................112

Section 6 Bus Controller

Figure 6.1

Block Diagram of Bus Controller ...........................................................................116

Figure 6.2

Overview of Area Divisions ...................................................................................127

Figure 6.3

CSn Signal Output Timing (n = 0 to 5)...................................................................130

Figure 6.4

On-Chip Memory Access Cycle .............................................................................131

Figure 6.5

Pin States during On-Chip Memory Access ...........................................................132

Figure 6.6

On-Chip Peripheral Module Access Cycle .............................................................132

Figure 6.7

Pin States during On-Chip Peripheral Module Access ...........................................133

Figure 6.8

Access Sizes and Data Alignment Control (8-Bit Access Space)...........................134

Figure 6.9

Access Sizes and Data Alignment Control (16-Bit Access Space).........................135

Figure 6.10 Bus Timing for 8-Bit 2-State Access Space............................................................136

Figure 6.11 Bus Timing for 8-Bit 3-State Access Space (Except Area 6) .................................137

Figure 6.12 Bus Timing for Area 6 and RTC.............................................................................138

Figure 6.13 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access) .....139

Figure 6.14 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access).......140

Figure 6.15 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) ...........................141

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