H8SSLASH2218 datasheet(39/750 Pages) RENESAS

39 / 750 page

Rev.6.00 Jun. 03, 2008 Page xxxvii of xlvi

REJ09B0074-0600

Figure 17.14 Memory Map in Programmer Mode....................................................................... 585

Figure 17.15 Power-On/Off Timing (Boot Mode)....................................................................... 589

Figure 17.16 Power-On/Off Timing (User Program Mode) ........................................................ 590

Figure 17.17 Mode Transition Timing

(Example: Boot Mode

→ User Mode ↔ User Program Mode).............................591

Section 18 Masked ROM

Figure 18.1 Block Diagram of On-Chip Masked ROM (64 kbytes).......................................... 593

Section 19 Clock Pulse Generator

Figure 19.1 Block Diagram of Clock Pulse Generator .............................................................. 595

Figure 19.2 Connection of Crystal Resonator (Example).......................................................... 600

Figure 19.3 Crystal Resonator Equivalent Circuit ..................................................................... 600

Figure 19.4 External Clock Input (Examples) ........................................................................... 601

Figure 19.5 External Clock Input Timing.................................................................................. 602

Figure 19.6 Example Connection of 32.768-kHz Quartz Oscillator.......................................... 603

Figure 19.7 Equivalence Circuit for 32.768-kHz Oscillator ...................................................... 603

Figure 19.8 Pin Handling when Subclock Not Required........................................................... 603

Figure 19.9 Example of PLL Circuit ......................................................................................... 604

Figure 19.10 Note on Board Design of Oscillator Circuit ........................................................... 605

Figure 19.11 Example of External Clock Switching Circuit ....................................................... 606

Figure 19.12 Example of External Clock Switchover Timing..................................................... 606

Section 20 Power-Down Modes

Figure 20.1 Mode Transition Diagram ...................................................................................... 609

Figure 20.2 Example of Flash Memory Module Stop Mode Usage .......................................... 616

Figure 20.3 Medium-Speed Mode Transition and Clearance Timing ....................................... 618

Figure 20.4 Software Standby Mode Application Example ...................................................... 621

Figure 20.5 Hardware Standby Mode Timing (Example) ......................................................... 622

Figure 20.6 Timing of Transition to Hardware Standby Mode ................................................. 622

Figure 20.7 Timing of Recovery from Hardware Standby Mode .............................................. 623

Section 22 Electrical Characteristics

Figure 22.1 Power Supply Voltage and Operating Ranges........................................................ 658

Figure 22.2 Output Load Circuit................................................................................................ 663

Figure 22.3 System Clock Timing ............................................................................................. 665

Figure 22.4 Oscillation Stabilization Timing............................................................................. 665

Figure 22.5 Reset Input Timing ................................................................................................. 667

Figure 22.6 Interrupt Input Timing............................................................................................ 667

Figure 22.7 Basic Bus Timing (Two-State Access)................................................................... 670

Figure 22.8 Basic Bus Timing (Three-State Access)................................................................. 671

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