H8SSLASH2218 datasheet(413/750 Pages) RENESAS

413 / 750 page

Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 365 of 698

REJ09B0074-0600

12.1.1

Block Diagram

Figure 12.1 shows the block diagram of the SCI_0. Figure 12.2 shows the block diagram of the

SCI_2.

RxD0

TxD0

PG1/

IRQ7

C/A

CKE1

SSE

SCK0

Clock

External clock

TEI

TXI

RXI

ERI

RSR:

RDR:

TSR:

TDR:

SMR:

Receive shift register

Receive data register

Transmit shift register

Transmit data register

Serial mode register

SCR:

SSR:

SCMR:

BRR:

SEMRA_0:

SEMRB_0:

Serial control register

Serial status register

Smart card mode register

Bit rate register

Serial extended mode register A_0

Serial extended mode register B_0

SCMR

SSR

SCR

SMR

SEMRA_0

SEMRB_0

control

transmission

and reception

Baud rate

generator

Average transfer

rate generator

10.667 MHz

· 115.152 kbps

· 460.606 kbps

16 MHz

· 115.196 kbps

· 460.784 kbps

· 720 kbps

· 921.569 kbps

24 MHz

· 115.132 kbps

· 460.526 kbps

· 720 kbps

· 921.053 kbps

BRR

TPU

TIOCC0

TIOCA1

TIOCA0

TIOCA2

Module data bus

RDR

TSR

RSR

Parity generation

Legend:

TDR

SCI transfer

clock generator

in TPU

Parity

check

φ/4

φ/16

φ/64

Figure 12.1 Block Diagram of SCI_0

H8S/2218 数据表(PDF) 413 Page - Renesas Technology Corp

H8S/2218 数据表(HTML) 413 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载