H8SSLASH2218 datasheet(596/750 Pages) RENESAS

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Section 15 A/D Converter

Rev.6.00 Jun. 03, 2008 Page 548 of 698

REJ09B0074-0600

15.8

Usage Notes

15.8.1

Module Stop Mode Setting

Operation of the A/D converter can be disabled or enabled using the module stop control register.

The initial setting is for operation of the A/D converter to be halted. Register access is enabled by

clearing module stop mode. For details, refer to section 20, Power-Down Modes.

15.8.2

Permissible Signal Source Impedance

This LSI's analog input is designed such that conversion precision is guaranteed for an input signal

for which the signal source impedance is 5 k

Ω or less. This specification is provided to enable the

A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time;

if the sensor output impedance exceeds 5 k

Ω, charging may be insufficient and it may not be

possible to guarantee A/D conversion precision. However, for A/D conversion in single mode with

a large capacitance provided externally, the input load will essentially comprise only the internal

input resistance of 10 k

Ω, and the signal source impedance is ignored. However, as a low-pass

filter effect is obtained in this case, it may not be possible to follow an analog signal with a large

differential coefficient (e.g., 5 mV/

Ωs or greater) (see figure 15.9). When converting a high-speed

analog signal, a low-impedance buffer should be inserted.

15.8.3

Influences on Absolute Precision

Adding capacitance results in coupling with GND, and therefore noise in GND may adversely

affect absolute precision. Be sure to make the connection to an electrically stable GND such as

AVSS.

Care is also required to insure that filter circuits do not communicate with digital signals on the

mounting board (i.e., acting as antennas).

20 pF

10 k

in =

15 pF

Sensor output

impedance

to 5 k

This LSI

Low-pass

filter C

to 0.1

μF

Sensor input

A/D converter

equivalent circuit

Figure 15.9 Example of Analog Input Circuit

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