H8SSLASH2218 datasheet(661/750 Pages) RENESAS

661 / 750 page

Section 20 Power-Down Modes

Rev.6.00 Jun. 03, 2008 Page 613 of 698

REJ09B0074-0600

20.1.2

Timer Control/Status Register (TCSR_1)

TCSR_1 controls the operation in power-down mode transition.

Bit

Bit Name

Initial Value

R/W

Description

7 to 5

⎯

All 0

⎯

Reserved

The write value should always be 0.

PSS

R/W

Prescaler Select

0: When the SLEEP instruction is executed in high-

speed mode or medium-speed mode, operation

shifts to sleep mode or software standby mode.

1: When the SLEEP instruction is executed in high-

speed mode or medium-speed mode, operation

shifts to sleep mode, watch mode, or subactive

mode.

When the SLEEP instruction is executed in

subactive mode, operation shifts to subsleep

mode, watch mode, or high-speed mode

TCSR_1 differs from other registers in being more

difficult to write to. The procedures for writing to

and reading this register are given below.

Write:

TCSR_1 must be written to by a word transfer

instruction. The upper byte of the written word must

contain H

′A5 and the lower byte must contain the

write data. (When the PSS bit is set to 1, the upper

byte of the written word must contain H'A510.)

Read:

TCSR_1 is read by the same procedure as for the

general registers.

3 to 0 —

All 0

—

Reserved

The write value should always be 0.

H8S/2218 数据表(PDF) 661 Page - Renesas Technology Corp

H8S/2218 数据表(HTML) 661 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载