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H8S/2218 数据表(PDF) 716 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 716 Page - Renesas Technology Corp |
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716 / 750 page  Section 22 Electrical Characteristics Rev.6.00 Jun. 03, 2008 Page 668 of 698 REJ09B0074-0600 22.4.3 Bus Timing Table 22.6 shows, Bus Timing. Table 22.6 Bus Timing Condition A: VCC = PLL VCC =Dr VCC =2.4 V to 3.6 V, Vref=2.4 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 6 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLL VCC =Dr VCC =2.7 V to 3.6 V, Vref=2.7 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 6 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = PLL VCC =Dr VCC =3.0 V to 3.6 V, Vref=3.0 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 6 MHz to 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition D: VCC = PLL VCC = Dr VCC = 3.0 V to 3.6 V, Vref = 3.0 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 16 MHz to 24 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Condition A Condition B Condition C, D Test Item Symbol Min. Max. Min. Max. Min. Max. Unit Conditions Address delay time tAD — 90 — 50 — 30 ns Address setup time tAS 0.5 × t cyc – 60 — 0.5 × t cyc – 30 — 0.5 × t cyc – 20 — ns Address hold time tAH 0.5 × t cyc – 30 — 0.5 × t cyc – 15 — 0.5 × t cyc – 8 — ns Figures 22.7, 22.8, 22.10 CS delay time tCSD — 90 — 50 — 30 ns Figures 22.7, 22.8 AS delay time tASD — 90 — 50 — 25 ns Figures 22.7, 22.8, 22.10 RD delay time 1 tRSD1 — 90 — 50 — 25 ns Figures 22.7, 22.8 RD delay time 2 tRSD2 — 90 — 50 — 25 ns Read data setup time tRDS 50 — 30 — 20 — ns Read data hold time tRDH 0 — 0 — 0 — ns Figures 22.7, 22.8, 22.10 Read data access time 2 tACC2 — 1.5 × t cyc – 90 — 1.5 × t cyc – 65 — 1.5 × t cyc – 35 ns Figure 22.7 |
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