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H8S/2218 数据表(PDF) 723 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 723 Page - Renesas Technology Corp |
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723 / 750 page  Section 22 Electrical Characteristics Rev.6.00 Jun. 03, 2008 Page 675 of 698 REJ09B0074-0600 22.4.4 Timing of On-Chip Supporting Modules Table 22.7 lists the timing of on-chip supporting modules. Table 22.7 Timing of On-Chip Supporting Modules Condition A: VCC = PLL VCC = Dr VCC = 2.4 V to 3.6 V, Vref = 2.4 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 6 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLL VCC = Dr VCC = 2.7 V to 3.6 V, Vref = 2.7 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 6 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = PLL VCC = Dr VCC = 3.0 V to 3.6 V, Vref = 3.0 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 6 MHz to 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition D: VCC = PLL VCC = Dr VCC = 3.0 V to 3.6 V, Vref = 3.0 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 16 MHz to 24 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Condition A Condition B Condition C, D Item Symbol Min. Max. Min. Max. Min. Max. Unit Test Conditions I/O port Output data delay time tPWD — 150 — 60 — 40 ns Figure 22.12 Input data setup time tPRS 80 — 50 — 30 — Input data hold time tPRH 50 — 50 — 30 — TPU Timer output delay time tTOCD — 150 — 60 — 40 ns Figure 22.13 Timer input setup time tTICS 60 — 40 — 30 — Timer clock input setup time tTCKS 60 — 40 — 30 — ns Figure 22.14 Single edge tTCKWH 1.5 — 1.5 — 1.5 — tcyc Timer clock pulse width Both edges tTCKWL 2.5 — 2.5 — 2.5 — |
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