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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2218 数据表(PDF) 736 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 736 Page - Renesas Technology Corp |
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736 / 750 page  Appendix Rev.6.00 Jun. 03, 2008 Page 688 of 698 REJ09B0074-0600 Port Name Pin Name MCU Operating Mode Power-on Reset Manual Reset Hardware Standby Mode Software Standby Mode or Watch Mode Bus Right Release State Program Execution State or Sleep Mode PF0/ BREQ 4 to 6 T keep T [BRLE=0] keep [BRLE=1] T T [BRLE=0] I/O port [BRLE=1] BREQ 7 T keep T keep keep I/O port PG4/ CS0*2 4 and 5 H 6 T keep T [DDR •OPE=0] T [DDR •OPE=1] H T [DDR=0] I/O port [DDR=1] CS0 (When sleep mode)H 7 T keep T keep keep I/O port PG3/ CS1*2 PG2/ CS2*2 PG1/ CS3 4 to 6 T keep T [DDR •OPE=0] T [DDR •OPE=1] H T [DDR=0] I/O port [DDR=1] CS1 to CS3 7 T keep T keep keep I/O port PG0* 3 4 to 7 T keep T keep keep I/O port Legend: H: High level L: Low level T: High impedance keep: Input port level is high impedance, and output port level is retained. DDR: Data direction register OPE: Output port enable WAITE: Wait port enable BRLE: Bus release enable Notes: 1. L (address input) in mode 4 or 5 2. Supported only by the H8S/2218 Group. 3. Supported only by the H8S/2212 Group. |
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